JTAG Debugging for Multi-core
The First JTAG Debugger Designed for Multi-core
Wind River ICE 2 is the first JTAG debugger optimized for visibility and control of your entire multi-core system. Embedded systems are getting more complex. Some run multiple operating systems over several cores, and in some cases these cores are supervised with Wind River Hypervisor. It’s critical that your JTAG debugger renders the entire system in one context (system level debugging of all application instances on many cores) all from a single JTAG debugging window. The ICE 2 JTAG debugger manages the hardware complexity behind the scenes, so you can focus on what matters most: tracking down bugs.
ICE 2 supports your current architecture and will extend with you into future architectures. Today ICE 2 supports the latest 32-bit and 64-bit processors based on leading architectures including ARM, Intel, MIPS, and PowerPC. And it's lab-ready, so your remote team members can access ICE 2 though a fast Gigabit Ethernet connection.
With ICE 2, you'll view operating system objects and set thread qualified breakpoints to pinpoint specific instances of logic running in your application. Set breakpoints on one or more cores, run diagnostic scripts, flash your board, and access key device information such as registers and cache.
| Front | Back |
![]() |
![]() |
| View the ICE 2 JTAG Debugger feature list for more details. | |
Watch the ICE 2 JTAG Debugger Video
Features
Multi-core Debugging
|
System-Level DebuggingAllows the user to resolve complex interactions among kernel, kernel modules, and applications. SMP systems can be represented by treating groups of cores as a single system including TOS awareness, kernel, kernel module, and application debug. |
Virtualized System Bring-UpVisibility into the hypervisor's object and virtual boards enables bring-up of a virtualized system with multiple guest OSes. |
Take Control of Your System
|
High-Performance Hardware Debugger
|
Highly Extensible Solution
|
Above and Beyond Board Bring-Up
|






